Apparatus and method for detecting word line leakage in memory devices

ABSTRACT

A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.

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BACKGROUND OF THE INVENTION

The present invention is directed generally to integrated circuits. Moreparticularly, the invention provides a method and apparatus for leakagecurrent testing for integrated circuit memory devices. Merely by way ofexample, the invention provides techniques for monitoring cell currentin a memory device for detecting word line leakage cause by processdefects. But it would be recognized that the invention has a muchbroader range of applicability. For example, the present invention canbe applied for testing other leakage conditions in integrated circuitmemory devices.

FIG. 1 is a block diagram illustrating a conventional memory device 100.As shown, memory device 100 includes a word line power generator 101coupled to memory sectors 110, 111, . . . , 119, etc. During memoryoperation, word line power generator 101 maintains a voltage required bythe word lines. For example, during a read operation, a read voltagelevel is required. As is known, leakage conditions often exist in amemory device. Conventionally, the leakage conditions are oftendetermined by monitoring power consumption of the memory device. Asdiscussed below, conventional techniques have various limitations, andan improved technique for memory leakage testing is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed generally to integrated circuits. Moreparticularly, the invention provides a method and apparatus for leakagecurrent testing for integrated circuit memory devices. Merely by way ofexample, the invention provides techniques for monitoring cell currentin a memory device for detecting word line leakage cause by processdefects. But it would be recognized that the invention has a muchbroader range of applicability. For example, the present invention canbe applied for testing other leakage conditions in integrated circuitmemory devices.

According to a specific embodiment, the invention provides a method fordetecting word line leakage in a memory device. The method includescoupling a first plurality of word lines in the memory device to avoltage source while coupling a second plurality of word lines in thememory device to a ground level voltage. Each of the second plurality ofword lines is adjacent to a corresponding one of the first plurality ofword lines. The method includes waiting for a first predetermined periodof time to allow the first plurality of word lines to reach apredetermined read voltage level. For example, the predetermined readvoltage level may be a word line voltage level for a memory readoperation. After the word lines have reached the predetermined voltagelevel, the first plurality of word lines are decoupled from the voltagesource. Then a wait time is elapsed for a second predetermined period oftime to allow the first plurality of word lines to discharge. At thispoint, the word line voltage level will have dropped due to intrinsicleakage such as junction leakage or due to extrinsic leakage conditionscaused by, for example, process defects. The method then includessensing a current associated with the first plurality of word lines andcomparing the current with a predetermined reference current. Thepredetermined reference current is selected for identifying a word lineleakage condition associated with the first plurality of word lines. Themethod further includes determining whether the word line leakagecondition exists. For example, if the sensed current is higher than thepredetermined reference current, then a leakage condition can bedetermined to exist. An example of this embodiment is shown in FIGS.10-13.

In a specific embodiment, the first plurality of word lines and thesecond plurality of word lines are selected from a memory array in thememory device. In an example, the memory array is coupled to the voltagesource through an array select switch. In an embodiment, each of thefirst and second plurality of word lines includes a word line driverdevice, which is capable of being coupled to the voltage source or tothe ground level voltage, for example, using decoding circuit known inthe art. In a specific example, the first plurality of word linesincludes even-numbered word lines in the memory device, and the secondplurality of word lines includes odd-numbered word lines in the memorydevice. In an embodiment, sensing the current includes performing amemory read operation to determine a current associated with a bit linecoupled to the first plurality of word lines. The parameters for testingare selected for specific testing conditions. For example, in anembodiment, the second predetermined period of time is selected to allowa voltage associated with the first plurality of word lines to bedischarged for identifying the word line leakage condition. In aparticular example, the second predetermined period of time is aboutseveral to hundreds μsec according to the detecting leakage criterionand word line capacitance. In an embodiment, the predetermined referencecurrent is selected to be higher than intrinsic leakage currentassociated with the first plurality of word lines as well as properworking range applies to sense amplifier. In another specificembodiment, the predetermined reference current is about 10 μA.

According to another embodiment, the invention provides a method fordetecting word line leakage in a memory device which includes a firstplurality of word lines. The method includes selecting a first word linefrom the first plurality of word lines in the memory device and couplingthe first word line in the memory device to voltage source whilegrounding the second plurality of word lines in the memory array. Themethod includes waiting for a first predetermined period of time toallow the first word line to reach a predetermined read voltage level.The method includes decoupling the first word line from the voltagesource and coupling the first word line to a floating voltage terminal.After waiting for a second predetermined period of time to allow thefirst word line to discharge, the method includes sensing a currentassociated with the first word line and comparing the sensed currentwith a predetermined reference current to identify a word line leakagecondition. The predetermined reference current is selected foridentifying a word line leakage condition. The method also includesdetermining whether the word line leakage condition exists. In aspecific embodiment, the plurality of word lines are coupled to thevoltage source through an array selection switch device. In anembodiment, coupling the first word line to a voltage source comprisesturning on a word line selection switch. In a specific embodiment,coupling the first word line to a floating voltage terminal comprisescoupling the first word line to a terminal of an off-state MOSFET. In anembodiment the second predetermined period of time is about several tohundreds μsec according to the detecting leakage criterion and word linecapacitance. In an embodiment, the predetermined reference current isabout 10 μA. An example of this embodiment is shown in FIGS. 14-17.

In yet another embodiment, the invention provides a method for detectingword line leakage in a memory device. The method includes coupling oneor more word lines in the memory device to a voltage source, whilecoupling at least a corresponding word line adjacent to each of the oneor more word lines to a ground voltage. The method includes waiting fora first predetermined period of time to allow the one or more word linesto reach a predetermined read voltage level before decoupling the one ormore word lines from the voltage source. The method includes waiting fora second predetermined period of time to allow the one or more wordlines to discharge, and then comparing a voltage associated with the oneor more word lines with a reference voltage, which is selected foridentifying a word line leakage condition associated with the one ormore word lines. The method further includes determining whether theword line leakage condition exists. In a specific embodiment, the memorydevice includes a switch device and a comparator circuit. The switchdevice couples the one or more word lines in the memory device to eitherthe voltage source or the comparator circuit in response to a memoryleakage testing command. In another embodiment, the memory deviceincludes a plurality of memory arrays. In this embodiment, the memorydevice further includes a switch device associated with each of theplurality of memory arrays and a comparator circuit. Each of the switchdevices couples the one or more word lines in a corresponding memoryarray to either the voltage source or the comparator circuit in responseto a memory leakage testing command. An example of this embodiment isshown in FIGS. 4-9.

Many benefits are achieved by way of the present invention overconventional techniques. For example, the present technique provides aneasy to use method that relies upon conventional technology. Embodimentsof the invention provide methods for detecting memory word line leakageconditions which may be difficult to detect using conventionaltechniques. In some embodiments, the method provides techniques todetecting word line leakage conditions by comparing a memory readcurrent with a predetermined reference current. In certain embodiments,the invention provides techniques for testing leakage conditionsassociated with a group of word lines or a single word line. In otherembodiments, the invention provides methods for testing word lineleakage conditions by monitoring word line voltage levels. Variousembodiments of the invention provide techniques that allow detection oflow level leakage conditions. Depending upon the embodiment, one or moreof these benefits may be achieved. These and other benefits will bedescribed in more detail throughout the present specification and moreparticularly below.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conventional block diagram illustrating a memory device;

FIG. 2 is a simplified schematic diagram of a memory device according toan embodiment of the present invention;

FIG. 3 is a simplified schematic diagram illustrating leakage conditionsin a memory device according to an embodiment of the present invention;

FIG. 4 is a simplified schematic diagram of a memory device for leakagetesting according to an embodiment of the present invention;

FIG. 5 is a simplified schematic diagram of a memory device for leakagetesting according to another embodiment of the present invention;

FIG. 6 is a simplified schematic diagram illustrating a method for wordline leakage testing in a memory device according to an embodiment ofthe present invention;

FIG. 7 is a simplified schematic diagram illustrating the methods forword line leakage testing in FIGS. 5 and 6;

FIG. 8 is another simplified diagram illustrating the methods for wordline leakage testing in FIGS. 5 and 6;

FIG. 9 is a simplified flow diagram of a method for word line testing ina memory device according to an embodiment of the present invention;

FIG. 10 is schematic diagram of a memory device for leakage testingaccording to an alternative embodiment of the present invention;

FIG. 11 is a simplified timing diagram illustrating a method for wordline leakage testing associated with the memory device 1000 in FIG. 10;

FIG. 12 is a simplified I-V diagram illustrating a method for word lineleakage testing associated with the memory device 1000 in FIG. 10;

FIG. 13 is simplified flow diagram of a method for word line testing ina memory device associated with the memory device 1000 in FIG. 10according to an embodiment of the present invention;

FIG. 14 is schematic diagram of a memory device for leakage testingaccording to yet another embodiment of the present invention;

FIG. 15 is a simplified timing diagram illustrating a method for wordline leakage testing associated with the memory device 1400 in FIG. 14;

FIG. 16 is a simplified I-V diagram illustrating a method for word lineleakage testing associated with the memory device 1400 in FIG. 14; and

FIG. 17 is simplified flow diagram of a method for word line testing ina memory device associated with the memory device 1400 in FIG. 14according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed generally to integrated circuits. Moreparticularly, the invention provides a method and apparatus for leakagecurrent testing for integrated circuit memory devices. Merely by way ofexample, the invention provides techniques for monitoring cell currentin a memory device for detecting word line leakage cause by processdefects. But it would be recognized that the invention has a muchbroader range of applicability. For example, the present invention canbe applied for testing other leakage conditions in integrated circuitmemory devices.

As discussed above with reference to memory device 100 in FIG. 1,conventional memory leakage conditions are often determined bymonitoring power consumption of the device. However, according toembodiments of the present invention, a memory device often hasintrinsic leakage conditions caused by, for example, inherent junctionleakage current. A certain amount of leakage current is often accepted,for example, as standby leakage current. In contrast, leakage conditionscaused by defects need to be identified, but the leakage path mayinclude a high impedance. Under such a condition, the leakage currentcaused by defects may be comparable in magnitude to the intrinsicleakage current. As a result conventional techniques may not distinguishbetween intrinsic leakage condition and leakage conditions caused bydefects. Therefore, an improved technique for memory word line leakagetesting is desired.

FIGS. 2 and 3 are simplified diagrams illustrating word line leakageconditions in a memory device according to an embodiment of the presentinvention. These diagrams are merely examples, which should not undulylimit the scope of the claims herein. One of ordinary skill in the artwould recognize other variations, modifications, and alternatives. FIG.2 is a simplified schematic diagram illustrating a memory device 200according to an embodiment of the present invention. As shown, memorydevice 200 includes one or more memory arrays, such as memory sectors0-N, designated as 210, . . . , 290, etc. As an example, sector 210includes word line driver 211 coupled to word line 212 and word linedriver 213 coupled to word line 214. An array selection switch device222, e.g., an MOSFET, is coupled to sectors 0-N. In FIG. 2, switchdevice 222 connects sectors 0-N to a voltage source 220 in response tocontrol signal SECB.

FIG. 3 is a simplified schematic diagram illustrating leakage conditionsin a memory device according to an embodiment of the present invention.As shown, word line driver 311 is coupled to word line 312, and wordline driver 313 is coupled to word line 314. Two leakage pathsassociated with word line 312 are shown in FIG. 3. A leakage path isshown to exist between word line 312 and substrate, and another leakagepath exists between word line 312 and the adjacent word line 314.Conventional techniques for detecting leakage conditions involvemonitoring leakage current from supply voltage to ground using a tester.However; under certain conditions, the leakage current may not be muchlarger than word line driver intrinsic leakage such as junction leakage.For example, if a high impedance path exists between word lines, theleakage current would be comparable with word line junction leakage.Then it would be difficult for conventional testing methods to determinewhether a word line leakage condition exists. Therefore, it is seen thatimproved techniques for detecting memory device leakage conditions aredesired.

FIG. 4 is a simplified schematic diagram of a memory device for leakagetesting according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. As shown, memorydevice 400 includes memory sectors 0-N, designated as 410, . . . , 490,etc. As an example, sector 410 includes word line driver 411 coupled toword line 412, and word line driver 413 coupled to word line 414. Anarray selection switch device 422, e.g., an MOSFET, is coupled tosectors 0-N. In a specific embodiment, array selection switch device 422is a PMOS device with its gate terminal connected to a ground voltagelevel (GND). Memory device 400 also includes a power source 420, acomparison circuit 430, and a test switch device 421 which connects thememory sectors to either the power source 420 or an input of thecomparison circuit 430, depending on a control signal (not shown). In anembodiment, the invention provides a method for testing memory device400. The method includes using switch device 421 to connect the memoryarray, including sectors 0-N, to power source 420 for a predeterminedlength of time to allow selected word lines in the memory array tocharge up to a voltage level PWR, for example, a read voltage level.Under a specific testing condition, adjacent word lines are biased topower source voltage level (PWR) and ground level (GND), respectively.For example, in FIG. 4, word line 412 is connected to PWR, word line 414is connected to GND. Then test switch device 421 connects the memoryarray to input 432 of the comparison circuit 430. After a certain periodof time to allow the word line voltages to discharge, the word linevoltage level at input 432 is compared to a reference voltage levelVref. Accordingly leakage condition can be determined. More details ofthe method are discussed further below.

FIG. 5 is a simplified schematic diagram of a memory device for leakagetesting according to another embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. As seen, memorydevice 500 is similar to memory device 400. In FIG. 5, memory device 500includes an array switch device and a test switch device for each of thememory sectors. For example, array switch device 522 and test switchdevice 521 are associated with sector 0, designated as 510. As anotherexample, array switch device 524 and test switch device 523 areassociated with sector N, designated as 590. The test switches connectthe respective memory sectors to either power source 520 or input 532 ofthe comparison circuit 530. In an embodiment of the invention, a methodis provided for testing memory circuit 500. Similar to the methoddiscussed above in connection with FIG. 4, the memory arrays are chargedto a read voltage level and then allowed to discharge, and then becompared to a reference voltage level. Since each memory sector isprovided with an array selection switch device and a test switch device,each sector can be tested separately in an embodiment. In anotherembodiment, a group of sectors can be tested simultaneously.

FIG. 6 is a simplified schematic diagram illustrating a method for wordline leakage testing in a memory device according to an embodiment ofthe present invention. In FIG. 6, memory sectors 510, . . . , 590, havebeen charged to a certain read voltage level, and are connected to input532 of comparison circuit 530. The voltage level at input 532 iscompared to a reference voltage level at 531. A method for determiningleakage condition is discussed below in reference to FIGS. 7 and 8.

FIG. 7 is a simplified schematic diagram illustrating the methods forword line leakage testing in FIGS. 5 and 6. As shown, capacitance 740(C_(total)) represent the total capacitance associated with the wordlines under testing. In FIG. 7, the word lines have been charged to apredetermined voltage level and now are allowed to discharge. The dottedline marked with I_(leakage) represents a potential leakage currentpath. FIG. 8 is a simplified diagram illustrating the methods for wordline leakage testing in FIGS. 5 and 6. In FIG. 8, the voltage level isplotted against time as the voltage is discharged. For example, line 803represents the voltage discharging with time for a memory array havingintrinsic junction leakage. Dotted line 804 represents the voltagedischarging with time for a memory array having word line leakagecondition in addition to intrinsic junction leakage. Initially, both 803and 804 are at voltage 801. After a predetermined time 805, marked as“Detection time” in FIG. 8, dotted line 804 drops below line 803,indicating the word line leakage condition. This leakage condition canbe identified by comparing the word line voltage level with a referencevoltage level 802 at time 805. In embodiments of the invention, thereference voltage level 802 and detection time can be selected tomonitor leakage conditions.

FIG. 9 is a simplified flow diagram 900 of a method for detecting wordline leakage in a memory device according to an embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims herein. One of ordinary skill inthe art would recognize other variations, modifications, andalternatives. With reference to FIG. 9, the method can be brieflyoutlined below.

-   -   1. (Process 910) Couple word line to voltage source;    -   2. (Process 920) Wait for word line to reach read voltage level;    -   3. (Process 930) Decouple word line from voltage source;    -   4. (Process 940) Wait for word line to discharge;    -   5. (Process 950) Compare word line voltage with reference        voltage; and    -   6. (Process 960) Determine word line leakage condition.

The method 900 shown in FIG. 9 is now discussed with reference to FIGS.4-8. In Process 910, the method includes coupling one or more word linesin the memory device to a voltage source. Depending on the embodiments,the word lines can be selected in different ways. For example, in thememory device 400 shown in FIG. 4, a word line from each memory sectorsis chosen. That is, word line 412 in sector 0, . . . , through word line492 in sector N are connected to voltage source 420 using switch device421. In another example, memory device 500 shown in FIG. 5, one wordline from one of the sectors is selected for leakage current testing.That is, word line 512 in sector 0 may be connected to voltage source520 using switch device 521 in for testing in one example. Then wordline 592 in sector N may be selected for testing subsequently. In yetanother example, shown in FIG. 6, more than one word line may beselected for testing simultaneously. The selected word lines are coupledto voltage source PWR which is designated as 420 in FIG. 4 and 520 inFIG. 5. According to embodiments of the invention, the method includesgrounding certain word lines adjacent to the selected word lines foreffective testing of inter-word lines leakage conditions. In Process920, the process includes waiting for a first predetermined period oftime to allow the one or more word lines to reach a predetermined readvoltage level. For example, the predetermined voltage level may be aread voltage level for a memory read operation. Of course, anothersuitable voltage levels can also be used. In Process 930, the word linesare decoupled from the voltage source. Then the word lines are allowedto discharge during a second predetermined period of wait time inProcess 940. Afterwards, in Process 950, the method includes comparing avoltage associated with the word lines with a reference voltage whichhas been selected for identifying a word line leakage conditionassociated with the selected word lines. The comparison can be carriedout using a comparator circuit, for example 430 in FIG. 4 or 530 in FIG.5. In this case, reference voltage 802 in FIG. 8 can be used to identifythe leakage condition. In Process 960, the method can be used todetermine whether the word line leakage condition exists. As shown inFIG. 8, after a wait period 805, discharge curve 804 indicates that theleakage associated with the word line or word lines under test is higherthan a reference word line 803.

In the method described above, various testing parameters can beselected for different testing conditions. For example, the first andsecond predetermined periods of time for charging up the word linesunder testing, as well reference voltage and current levels may bedetermined experimentally. In a particular example, the secondpredetermined period of time is about several to hundreds μsec accordingto the detecting leakage criterion and word line capacitance. In anembodiment, the predetermined reference current is selected to be higherthan intrinsic leakage current associated with the first plurality ofword lines as well as proper working range applies to the senseamplifier. In another specific embodiment, the predetermined referencecurrent is about 10 μA. Of course, there can be other variations,modifications, and alternatives.

The above sequence of processes provides word line leakage detectionmethod according to an embodiment of the present invention. As shown,the method uses a combination of steps including a way of charging upselected word lines, waiting for the word lines to discharge, and thenobserving the word line voltage to determine a leakage condition. Otheralternatives can also be provided where steps are added, one or moresteps are removed, or one or more steps are provided in a differentsequence without departing from the scope of the claims herein. Furtherdetails of the present method can be found throughout the presentspecification and more particularly below.

FIG. 10 is schematic diagram of a memory device for leakage testingaccording to an alternative embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. As shown, memorydevice 1000 includes one or more memory arrays, for example, memorysector 0, designated as 1010 in FIG. 10. Memory sector 1010 includes aplurality of word lines, each of which coupled to a word line driverdevice. For example, word line driver 1011 is coupled to word line 1012,and word line driver 1013 is coupled to word line 1014. An arrayselection switch device 1022, e.g., an MOSFET, is coupled to sector 1010and a power source 1020. Array selection switch device 1022 connectssector 1010 to power source 1020 in response to a control signal,designated as SEC0B in FIG. 10. In alternative embodiments, memorydevice may include multiple arrays arranged in sectors. In anembodiment, a sector may be connected to a specific array selectionswitch device. In other embodiments, two or more arrays may be connectedto an array selection switch.

FIG. 11 is a simplified timing diagram illustrating a method for wordline leakage testing according to an alternative embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims herein. One of ordinary skill inthe art would recognize other variations, modifications, andalternatives. The method is discussed below with reference to the memorydevice 1000 in FIG. 10. The method includes activating control signalSEC0B to connect the memory array 1010 to power source 1020 for apredetermined length of time to allow selected word lines in the memoryarray to charge up to a voltage level PWR, for example, a read voltagelevel. Under a specific testing condition, adjacent word lines arebiased to power source voltage level (PWR) and ground level (GND),respectively. For example, in FIG. 10, even-numbered word lines such asword line WL 0 (1012) are connected to PWR, whereas odd-numbered wordlines such as word line WL 1 (1014) are connected to GND. After theselected word lines are charged up to the predetermined level, controlsignal SEC0B is deactivated, and the word line voltages to dischargeduring a period of wait time, as marked between the dotted lines T₁ andT₂ in the timing diagram in FIG. 11. Then, a memory read operation isstarted by the READEN control signal. Word line leakage conditions canbe determined as discussed below.

FIG. 12 is a simplified I-V diagram illustrating a method for word lineleakage testing according to an embodiment of the invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognizeother variations, modifications, and alternatives. As shown, memoryarray read current is plotted against word line voltage. Point Arepresents the read current when the word line voltage is at the fullread voltage level. Point B represents the cell current I_(B) when theword line voltage has dropped slightly due to intrinsic junctionleakages, for example. Point C represents the cell current I_(C) whenthe word line voltage has dropped more due to additional word lineleakage conditions caused by, for example, defects. In an embodiment ofthe invention, a reference current level I_(ref) is selected to identifyword line leakage conditions. In a specific embodiment, a word lineleakage condition is identified if the read current is less thanI_(ref). Of course, there can be other variations, modifications, andalternatives. More details of the method for testing word line leakageconditions are discussed below with reference to FIGS. 10-13.

FIG. 13 is a simplified flow diagram 1300 of a method for detecting wordline leakage in a memory device according to another embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims herein. One of ordinary skill inthe art would recognize other variations, modifications, andalternatives. With reference to FIG. 13, the method can be brieflyoutlined below.

-   -   1. (Process 1310) Connect selected word lines to voltage supply;    -   2. (Process 1320) Wait for selected word lines to reach a        predetermined read voltage level;    -   3. (Process 1330) Decouple the word lines from the voltage        source;    -   4. (Process 1340) Wait for word lines to discharge;    -   5. (Process 1350) Sense a current associated with the word        lines;    -   6. (Process 1360) Compare the sensed current with reference        current; and    -   7. (Process 1370) Determine word line leakage condition.

As shown, in Process 1310, the method includes coupling a firstplurality of word lines in the memory device to a voltage source, whilecoupling a second plurality of word lines in the memory device to aground level voltage. Each of the second plurality of word lines isadjacent to a corresponding one of the first plurality of word lines.Depending on the embodiments, the word lines can be selected indifferent ways. For example, in the memory device 1000 shown in FIG. 10,even-numbered word lines from the memory sector are coupled to thevoltage source, whereas odd-numbered word lines in the memory sector arecoupled to a ground level voltage. In another example, only one wordline may be coupled to the voltage source, whereas an adjacent word lineis coupled to a ground level voltage. In FIG. 10, the selected wordlines are coupled to voltage source PWR 1020. In Process 1320, theprocess includes waiting for a first predetermined period of time toallow the first plurality of word lines to reach a predetermined readvoltage level. For example, the predetermined voltage level may be aread voltage level for a memory read operation, as shown by the “ReadLevel” voltage associated with EVEN WL in FIG. 1100. Of course, anothersuitable voltage levels can also be used. In Process 1330, the wordlines are decoupled from the voltage source. Then the word lines areallowed to discharge during a second predetermined period of wait timein Process 1340, shown as T₁ and T₂ in FIG. 1100. Afterwards, in Process1350, the method includes sensing a current associated with the selectedword lines. In Process 1360, the method includes comparing the sensedcurrent with a predetermined reference current. The predeterminedreference current is selected for identifying a word line leakagecondition associated with the first plurality of word lines. In Process1370, the method can be used to determine whether the word line leakagecondition exists. For example, in FIG. 12, the reference current isshown as I_(ref), and a sensed current below I_(ref) is identified as aleakage condition.

In the method described above, various testing parameters can beselected for different testing conditions. For example, the first andsecond predetermined periods of time for charging up the word linesunder testing, as well reference voltage and current levels may bedetermined experimentally. In a particular example, the secondpredetermined period of time is about several to hundreds μsec accordingto the detecting leakage criterion and word line capacitance. In anembodiment, the predetermined reference current is selected to be higherthan intrinsic leakage current as well as proper working range appliesto sense amplifier. In another specific embodiment, the predeterminedreference current is about 10 μA. Of course, there can be othervariations, modifications, and alternatives.

The above sequence of processes provides word line leakage detectionmethod according to an embodiment of the present invention. As shown,the method uses a combination of steps including a way of charging upselected word lines, waiting for the word lines to discharge, and thensensing a current associated with the word line under test to determinea leakage condition. Other alternatives can also be provided where stepsare added, one or more steps are removed, or one or more steps areprovided in a different sequence without departing from the scope of theclaims herein. Further details of the present method can be foundthroughout the present specification and more particularly below.

FIGS. 14-16 are simplified diagrams illustrating a method for testingword line leakage conditions according to another embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims herein. One of ordinary skill inthe art would recognize other variations, modifications, andalternatives. FIG. 14 is schematic diagram of a memory device forleakage testing according to an embodiment of the present invention.Memory device 1400 is similar to memory device 1000, but also includescapabilities for testing individual word lines. As shown, memory device1400 includes one or more memory arrays, for example, memory sector 0,designated as 1410. Memory sector 1410 includes a plurality of wordlines, each of which coupled to a word line testing selection device.For example, word line 1411 is coupled to word line testing selectiondevice which includes PMOS transistor 1412 and NMOS transistor 1413responsive to control signal WLSEL, and NMOS transistor 1414 responsiveto control signal WLFLOATB. An array selection switch device 1422, e.g.,an MOSFET, is coupled to sector 1410 and a power source 1420. Arrayselection switch device 1422 connects sector 1010 to power source 1420in response to a control signal, designated as SEC0B in FIG. 14.According to a specific embodiment, the invention provides a method fortesting word line leakage in memory device 1400, as discussed below.

The method includes charging up a selected word line in a memory array,while other word lines in the array are grounded. Then the selected wordline is connected to a floating terminal and allowed to discharge. Aftera predetermined wait time, a memory read operation is carried out todetermine a leakage condition. For example, in FIG. 14, WL 0 (1411) isselected for testing by turning on PMOS 1412 and turning off NMOS 1413.WL 0 is connected to the floating terminal by turning off PMOS 1412,turning on NMOS 1413, and turning off NMOS 1414. WL 0 (1411) is thenconnected to a drain terminal of the turned-of NMOS 1414.

FIG. 15 is a simplified timing diagram and FIG. 16 is a simplified I-Vdiagram illustrating the method for word line leakage testing associatedwith the memory device 1400 in FIG. 14. More details of the method fortesting word line leakage conditions are discussed below with referenceto FIGS. 14-17.

FIG. 17 is a simplified flow diagram 1700 of a method for detecting wordline leakage in a memory device according to an embodiment of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims herein. One of ordinary skill inthe art would recognize other variations, modifications, andalternatives. With reference to FIG. 17, the method can be brieflyoutlined below.

-   -   1. (Process 1710) Select a first word line from the plurality of        word lines in the memory device;    -   2. (Process 1720) Couple the first word line in the memory        device to voltage source while grounding unselected word lines        in the memory array;    -   3. (Process 1730) Wait for a first predetermined period of time        to allow the first word line to reach a predetermined read        voltage level;    -   4. (Process 1740) Couple the first word line to a floating        voltage terminal;    -   5. (Process 1750) Wait for a second predetermined period of time        to allow the first word line to discharge;    -   6. (Process 1760) Sense a current associated with the first word        line;    -   7. (Process 1770) Compare the sensed current with a        predetermined reference current, the predetermined reference        current being selected for identifying a word line leakage        condition; and    -   8. (Process 1780) Determine whether the word line leakage        condition exists.

As shown, in Process 1710 the method includes selecting a first wordline from the plurality of word lines in the memory device. Referring toFIG. 14 as an example, WL 0 (1411) is selected for testing. In Process1720, the method coupling the first word line in the memory device tovoltage source while grounding unselected word lines in the memoryarray. Referring to FIG. 14 as an example, WL0 (1411) is selected fortesting, and WL Ito WL (M) are connected to a ground voltage. In Process1730, the method includes waiting for a first predetermined period oftime to allow the first word line to reach a predetermined read voltagelevel. In Process 1740, the method includes coupling the first word lineto a floating voltage terminal and, in Process 1750, waiting for asecond predetermined period of time to allow the first word line todischarge. For example, the second predetermined period of time isindicated as T_(delay2) in FIG. 15. In Process 1760, a memory readoperation is performed for sensing a current associated with the firstword line. In Process 1770, the sense current is compared with apredetermined reference current, which has been selected for identifyinga word line leakage condition. In Process 1780, the method includesdetermining whether the word line leakage condition exists. The variouscurrents associated with word line testing are shown in FIG. 16. Similarto discussions associated with FIG. 12, the sense current is compared toa reference current I_(ref) to determine a leakage condition.

In the method described above, various testing parameters can beselected for different testing conditions. For example, the first andsecond predetermined periods of time for charging up the word linesunder testing, as well reference voltage and current levels may bedetermined experimentally. In a particular example, the secondpredetermined period of time is about several to hundreds μsec accordingto the detecting leakage criterion and word line capacitance. In anembodiment, the predetermined reference current is selected to be higherthan intrinsic leakage current as well as proper working range appliesto sense amplifier. In another specific embodiment, the predeterminedreference current is about 10 μA. Of course, there can be othervariations, modifications, and alternatives.

The above sequence of processes provides word line leakage detectionmethod according to an embodiment of the present invention. As shown,the method uses a combination of steps including a way of charging upselected word lines, waiting for the word lines to discharge, and thenobserving the word line voltage to determine a leakage condition. Otheralternatives can also be provided where steps are added, one or moresteps are removed, or one or more steps are provided in a differentsequence without departing from the scope of the claims herein.

While the preferred embodiments of the invention have been illustratedand described, it will be clear that the invention is not limited tothese embodiments only. Numerous modifications, changes, variations,substitutions and equivalents will be apparent to those skilled in theart without departing from the spirit and scope of the invention asdescribed in the claims.

1. A method for detecting word line leakage in a memory device, themethod comprising: coupling a first plurality of word lines in thememory device to a voltage source while coupling a second plurality ofword lines in the memory device to a ground level voltage, each of thesecond plurality of word lines being adjacent to a corresponding one ofthe first plurality of word lines; waiting for a first predeterminedperiod of time to allow the first plurality of word lines to reach apredetermined read voltage level; decoupling the first plurality of wordlines from the voltage source; waiting for a second predetermined periodof time to allow the first plurality of word lines to discharge; sensinga current associated with the first plurality of word lines; andcomparing information related to the current with information related toa predetermined reference current, the predetermined reference currentbeing selected for identifying a word line leakage condition associatedwith the first plurality of word lines.
 2. The method of claim 1 whereinthe first plurality of word lines and the second plurality of word linesare selected from a memory array in the memory device, the memory arraybeing coupled to the voltage source through an array select switch. 3.The method of claim 2 wherein each of the first and second plurality ofword lines comprises a word line driver device, the word line driverdevice capable of being coupled to the voltage source, the word linedrive device also capable of being coupled to the ground level voltage.4. The method of claim 2 wherein the first plurality of word linescomprises even-numbered word lines in the memory device, and wherein thesecond plurality of word lines comprises odd-numbered word lines in thememory device.
 5. The method of claim 1 wherein sensing the currentcomprises performing a memory read operation to determine a currentassociated with a bit line coupled to the first plurality of word lines.6. The method of claim 1 wherein the second predetermined period of timeis selected to allow a voltage associated with the first plurality ofword lines to be discharged for identifying the word line leakagecondition.
 7. The method of claim 1 wherein the second predeterminedperiod of time is about several to hundreds μsec according to thedetecting leakage criterion and word line capacitance.
 8. The method ofclaim 1 the predetermined reference current being higher than intrinsicleakage current associated with the first plurality of word lines. 9.The method of claim 1 wherein the predetermined reference current isabout 10 μA based on sense amplifier operation range.
 10. A method fordetecting word line leakage in a memory device which includes a firstplurality of word lines, the method comprising: selecting a first wordline from the first plurality of word lines in the memory device, theunselected word lines in the first plurality of word lines beingdesignated as the second plurality of word line; coupling the first wordline in the memory device to voltage source while grounding the secondplurality of word lines in the memory array; waiting for a firstpredetermined period of time to allow the first word line to reach apredetermined read voltage level; decoupling the first word line fromthe voltage source; coupling the first word line to a floating voltageterminal; waiting for a second predetermined period of time to allow thefirst word line to discharge; sensing a current associated with thefirst word line; and comparing information related to the sensed currentwith information related to a predetermined reference current, thepredetermined reference current being selected for identifying a wordline leakage condition.
 11. The method of claim 10 wherein the pluralityof word lines are coupled to the voltage source through an arrayselection switch device.
 12. The method of claim 10 wherein coupling thefirst word line to a voltage source comprises turning on a word lineselection switch.
 13. The method of claim 10 wherein coupling the firstword line to a floating voltage terminal comprises coupling the firstword line to a terminal of an off-state MOSFET.
 14. The method of claim10 wherein the second predetermined period of time is about several tohundreds μsec according to the detecting leakage criterion and word linecapacitance.
 15. The method of claim 10 wherein the predeterminedreference current is about 10 μA based on sense amplifier operationrange.
 16. A method for detecting word line leakage in a memory device,the method comprising: coupling one or more word lines in the memorydevice to a voltage source while coupling at least a correspondingadjacent word line to a ground voltage; waiting for a firstpredetermined period of time to allow the one or more word lines toreach a predetermined read voltage level; decoupling the one or moreword lines from the voltage source; waiting for a second predeterminedperiod of time to allow the one or more word lines to discharge; andcomparing information related to a voltage associated with the one ormore word lines with information related to a reference voltage, thereference voltage being selected for identifying a word line leakagecondition associated with the one or more word lines.
 17. The method ofclaim 16 wherein the memory device includes a switch device and acomparator circuit, the switch device coupling the one or more wordlines in the memory device to either the voltage source or thecomparator circuit in response to a memory leakage testing commandsignal.
 18. The method of claim 16 wherein the memory device comprises aplurality of memory arrays, the memory device further including a switchdevice associated with each of the plurality of memory arrays and acomparator circuit, each of the switch devices coupling the one or moreword lines in a corresponding memory array to either the voltage sourceor the comparator circuit in response to a memory leakage testingcommand signal.